FIGS. 1A and 1B illustrate a high performance, low power domino SRAM design including multiple local cell groups such as that shown in U.S. Pat. No. 6,657,886, the entire contents of which are incorporated herein by reference. As shown in FIG. 1A, each cell group includes multiple SRAM cells 1–N and local true and complement bitlines LBLT and LBLC. Each SRAM cell includes a pair of inverters that operate together in a loop to store true and complement (T and C) data. The local true bitline LBLT and the local complement bitline LBLC are connected to each SRAM cell by a pair of wordline N-channel field effect transistors (NFETs) to respective true and complement sides of the inverters. A WORDLINE provides the gate input to wordline NFETs. A particular WORDLINE is activated, turning on respective wordline NFETs to perform a read or write operation.
As shown in FIG. 1B, the prior art domino SRAM includes multiple local cell groups 1–M. Associated with each local cell group are precharge true and complement circuits coupled to the respective local true and complement bitlines LBLT and LBLC, write true and write complement circuits, and a local evaluate circuit. Each of the local evaluate circuits is coupled to a global bitline labeled 2ND STAGE EVAL and a second stage inverter that provides output data or is coupled to more stages. A write predriver circuit receiving input data and a write enable signal provides write true WRITE T and write complement WRITE C signals to the write true and write complement circuits of each local cell group.
A read occurs when a wordline is activated. Since true and complement (T and C) data is stored in the SRAM memory cell, either the precharged high true local bitline LBLT will be discharged if a zero was stored on the true side or the precharged high complement bitline LBLC will be discharged if a zero was stored on the complement side. The local bitline, LBLT or LBLC connected to the one side will remain in its high precharged state. If the true local bitline LBLT was discharged then the zero will propagate through one or more series of domino stages eventually to the output of the SRAM array. If the true local bitline was not discharged then no switching through the domino stages will occur and the precharged value will remain at the SRAM output.
To perform a write operation, the wordline is activated as in a read. Then either the write true WRITE T or write complement WRITE C signal is activated which pulls either the true or complement local bitline low via the respective write true circuit or write complement circuit while the other local bitline remains at its precharged level, thus updating the SRAM cell.
During a write operation, the wordline is activated as in a read. The cell will begin to discharge the bitline corresponding to the side of the cell that has a zero stored. If the write operation is meant to change the state of the cell, the write circuit will discharge the bitline opposite of the one that the cell has begun to discharge. Thus the bitline being discharged by the cell can trigger a read before the cell is updated by the write operation, particularly if the write circuit response is slow. Such an occurrence can produce inaccurate results and is referred to as a false read. There is a need in the art for a circuit for driving write operations that also suppresses false reads.